The present invention relates to metal oxide semiconductor (MOS) image sensors and, more particularly, an analog delay line for a MOS image sensor.
Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. In the field of imaging, the charge coupled device (CCD) sensor has made possible the manufacture of relatively low-cost and small hand-held video cameras. Nevertheless, the solid-state CCD integrated circuits needed for imaging are relatively difficult to manufacture, and therefore are expensive. In addition, because of the differing processes involved in the manufacture of CCD integrated circuits relative to MOS integrated circuits, the signal processing portion of the imaging sensor has typically been located on a separate integrated chip. Thus, a CCD imaging device includes at least two integrated circuits: one for the CCD sensor and one for the signal processing logic.
Some of the further drawbacks of CCD technology are discussed in xe2x80x9cActive Pixel Sensorsxe2x80x94Are CCD""s Dinosaurs?xe2x80x9d by E. R. Fossum, Proceedings of the SPIExe2x80x94The International Society for Optical Engineering, Vol. 1900, 1993, pp. 2-14. As stated therein, xe2x80x9c[a]lthough CCDs have become a technology of choice for present-day implementation of imaging and spectroscopic instruments due to their high-sensitivity, high quantum efficiency, and large format, it is well-known that they are a particularly difficult technology to master. The need for near-perfect charge transfer efficiency makes CCDs (1) radiation xe2x80x98soft,xe2x80x99 (2) difficult to reproducibly manufacture in large array sizes, (3) incompatible with the on-chip electronics integration requirements of miniature instruments, (4) difficult to extend the spectral responsivity range through the use of alternative materials, and (5) limited in their readout rate.xe2x80x9d
An alternative low-cost technology to CCD integrated circuits is the metal oxide semiconductor (MOS), integrated circuit. Not only are imaging devices using MOS technology less expensive to manufacture relative to CCD imaging devices, for certain applications MOS devices are superior in performance. For example, the pixel elements in a MOS device can be made smaller and therefore provide a higher resolution than CCD image sensors.
Examples of MOS imaging devices are detailed in xe2x80x9cA xc2xc Inch Format 250 K Pixel Amplified MOS Image Sensor Using CMOS Processxe2x80x9d by Kawashima et al., IEDM 93-575 (1993), and xe2x80x9cA Low Noise Line-Amplified MOS Imaging Devicesxe2x80x9d by Ozaki et al., IEEE Transactions on Electron Devices, Vol. 38, No. 5, May 1991. In addition, U.S. Pat. No. 5,345,266 to Denyer, titled xe2x80x9cMatrix Array Image Sensor Chip,xe2x80x9d describes a MOS image sensor. The devices disclosed in these-publications provide a general design approach to MOS imaging devices. In addition, MOS approaches to color imaging devices are described in xe2x80x9cColor Filters and Processing Alternatives for One-Chip Cameras,xe2x80x9d by Parulski, IEEE Transactions on Electron Devices, Vol. ED-32, No. 8, August 1985, and xe2x80x9cSingle-Chip Color Cameras With Reduced Aliasingxe2x80x9d by Imaide et al., Journal of Imaging Technology, Vol. 12, No. 5, October 1986, pp. 258-260.
In the movement from CCD- to MOS-based implementations that can be fabricated on a single MOS chip, certain concepts from the CCD technology have not transferred smoothly. One example is related to the external CCD-delay line that is still used in many image processors to obtain the necessary signals from two rows of pixels simultaneously. The need to process two rows of pixels simultaneously is related to the processing of signals from complementary color filter patterns, as is described in more detail below.
In most solid-state color image sensors, a complementary color filter pattern is used. Arrays of pixels may be made to detect color by being covered with a regular pattern of color filter patches, known as a color filter pattern. The filter patches can be fabricated directly on the sensor or on a transparent substrate which is later cemented to the chip. Color filter patterns may include colors such as red (R), green (G), blue (B), yellow (Ye), cyan (Cy) and magenta (Mg). The pixels beneath the color filter pattern emit signals when they are exposed to the type of light indicated by the color filter patch. Thus, a red signal could be obtained from a pixel beneath a red filter patch, a blue signal could come from a pixel beneath a blue filter patch, and so on.
However, some image sensors do not obtain the standard red, green and blue signals from red, green and blue filtered pixels. Instead, they use combinations of other colors to obtain the standard ones. For example, red (R) can be formed according to the equation R=(W+Ye)xe2x88x92(G+Cy), where the color filter pixel signals are W=white, Ye=yellow, G=green, and Cy=cyan. In cases such as this, the four pixel signals being processed are obtained from a 2xc3x972 block of one of each type of pixel sensor, rather than a 1xc3x974 row of pixel sensors which would tend to distort the color image. The 2xc3x972 block presents a problem for standard pixel scanning methods because standard methods scan each row, one at a time. In contrast, the 2xc3x972 block of pixels comes from sections of two separate rows. Thus, the system cannot process the data as it scans each row. It must wait until the next row is also scanned to obtain the remaining information that it needs, and it must somehow save the data from the previous row until it does so.
Just as the color signals in such cases can be a combination of the signals from a 2xc3x972 pixel block, the chrominance signal, which correlates to the color of the image, is also sometimes obtained from a combination of signals from pixels in two separate rows. In fact, this is the case for the chrominance signal in many systems, even those in which R, G and B filters are used to obtain the color signals directly. Therefore, it is required in such systems to somehow have the data from two separate rows available at the same time so that the required combinations can be processed.
A standard method for making the data from two separate rows available at the same time is to use a delay line. The delay line holds the data from one row until the next row can be scanned to provide the needed information. One simple type of delay line is a digital delay line. The digital delay line stores digital values representative of the pixel signals from a given row. Digital delay lines are commonly used in MOS imaging devices. However, in order to use a digital delay line, the pixel signals must necessarily be first converted to digital values before they are stored in the digital delay line. One of the problems with converting the pixel signals to digital values at this early stage, is that the analog-to-digital processing requires a significant amount of power. This is an undesirable characteristic in certain implementations of imaging devices.
An alternative to a digital delay line that has been used in most prior art CCD devices is an analog CCD delay line. FIG. 1 illustrates a general CCD delay line of the prior art. As illustrated in FIG. 1, signals from a sensor array are received via a signal line V0 by a CCD delay line 10. The CCD delay line 10 delays the pixel signals as it takes time for the signals to cascade down the cells of the CCD delay line. The CCD delay line is controlled so that after a first row of pixels has been read into the CCD delay line, the signal from the first pixel of the first row is read out from the CCD delay line on the signal line V1 at the same time that the pixel signal from the first pixel of the second row is being received on the signal line V0. In this manner, the signal processing circuitry 12 receives the signals from adjacent pixels in two different rows at the same time. In this manner, a 2xc3x972 pixel block may be obtained for signal processing, as described above.
In the movement from CCD- to MOS-based implementations, methods of implementing the circuitry have been sought that can easily be fabricated on a single MOS chip. The approach of using an external CCD delay line device in the color image sensors, which was carried over from the old CCD technology, has inherently required the use of CCD components that are external to the circuit and that are sometimes required to be on a separate chip, in addition to increasing the relative complexity of the implementation. It is a general principle that power consumption and cost would decrease if the number of chips and complex components necessary to accomplish the task were decreased. The present invention is directed toward an improved analog delay line that can be fabricated using MOS technology, and which can therefor be integrated on a single-chip with the MOS sensor array.
The present invention is directed to an analog delay line for a MOS image sensor which allows the simultaneous reading of pixel signals from two adjacent rows of pixels so that combinations of signals from pixels in adjacent rows may be obtained. The delay line includes a set of storage capacitors, a first set of switches for selectively placing signals from a row of the pixel array on the first set of storage capacitors, and a second set of switches for selectively reading out the signals from the storage capacitors. In one embodiment of the invention, two delay lines are utilized, such that the signals from one row of the pixel array can be being stored in one of the delay lines, while the signals from the previous row of pixels that were previously stored in the other delay line can be being read out. In another embodiment of the invention, a single delay line is used, in combination with a single pixel delay circuit. In the second embodiment, the signals that were previously stored in the delay line from the previous row are read out one at a time into the single pixel delay circuit, just ahead of when the new signals from the pixels of the next row are being read into the delay line. In this manner, the pixel signals from the single pixel delay circuit can be being output at the same time that the pixel signals from the next row are both being stored in the delay line, and are available for signal processing. Thus, signals from adjacent pixels in adjacent rows can be being read out simultaneously, as is the goal of the invention.
The single pixel delay circuit includes a set of two storage capacitors, a set of two input switches for selectively placing pixel signals on the two storage capacitors, and a set of two output switches for selectively reading out the pixel signals that were previously stored on the two storage capacitors. Various amplifiers and buffers are used in combination with the delay line and single pixel delay circuit structures, so as to effectively transfer the pixel signal charges. The capacitors, MOS switches, buffers, and amplifiers of the reading structure are easily fabricated as part of a MOS image sensor on a single chip.